About the role
We’re looking for power integrity engineers to ensure that power is delivered and stable at all levels: rack/tray, package, die, core.
Ideal Background:
* Experience with large die, high TDP chip PDN analysis and design * Experience with advanced node (7nm and lower) chip PDN analysis and design * Ability to work with package architects to determine best passives design within a given set of constraints * Ability to work with ASIC and microarchitecture team to hit power integrity goals given manufacturing design constraints
Nice to Have:
* Experience with WSI (wafer-scale integration) systems * Board and system-level power delivery network analysis and design * Low voltage die power delivery network analysis and design * Many voltage domain power delivery network design and analysis * IVR based design experience